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products and specifications discussed herein ar e subject to change by micron without notice. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 1 ?2006 micron technology, inc. all rights reserved. ddr2 sdram vlp rdimm mt36hvs25672(p) ? 2gb mt36hvs51272(p) ? 4gb mt36hvzs51272(p) ? 4gb for component data sheets, refer to micron?s web site: www.micron.com features ? 240-pin, very low profile registered dual in-line memory module (vlp rdimm) ? compatible with atca form factors ? fast data transfer rates: pc2-4200, pc2-5300, or pc2-6400 ? supports ecc error detection and correction ?v dd = v dd q = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? dual rank using twindie ? devices ? multiple internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths (bl): 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? serial presence-det ect (spd) with eeprom ? gold edge contacts figure 1: 240-pin vlp rdimm (atca form factor) notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency; registered mode will add one clock cycle to cl. 3. not recommended for new designs. options marking ? full module heat spreader (4gb density only) z ?parity p ? operating temperature 1 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 240-pin dimm (pb-free) y ? frequency/cas latency 2 ? 2.5ns @ cl = 5 (ddr2-800) -80e ? 2.5ns @ cl = 6 (ddr2-800) -800 ? 3.0ns @ cl = 5 (ddr2-667) -667 ? 3.75ns @ cl = 4 (ddr2-533) 3 -53e p c b hei g ht: 17.9mm (0.705in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 ? 800 533 ? 12.5 12.5 55 -800 pc2-6400 800 667 533 ? 15 15 55 -667 pc2-5300 ? 667 533 400 15 15 55 -53e pc2-4200 ? ? 533 400 15 15 55
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 2 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features notes: 1. the data sheets for the base devi ces can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for curre nt revision codes. example: mt36hvs51272py-667d1 . table 2: addressing parameter 2gb 4gb refresh count 8k 8k row address 16k a[13:0] 16k a[13:0] device bank address 4 ba[1:0] 8 ba[2:0] device configuration 1gb twindie (2 56 meg x 4) 2gb twindie (512 meg x 4) column address 2k a[11, 9:0] 2k a[11, 9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters ? 2gb modules base device: mt47h256m4thk, 1 1gb twindie ddr2 sdram part number ,2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvs25672(p)y-667__ 2gb 256 meg x 72 5.3 gb/s 3.0n s/667 mt/s 5-5-5 mt36hvs25672(p)y-53e__ 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 table 4: part numbers and timing parameters ? 4gb modules base device: mt47h512m4thn, 1 2gb twindie ddr2 sdram part number ,2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvs51272(p)y-80e__ 4gb 512 meg x 72 6.2 gb/s 2.5n s/800 mt/s 5-5-5 mt36hvs51272(p)y-800__ 4gb 512 meg x 72 6.2 gb/s 2.5n s/800 mt/s 6-6-6 mt36hvs51272(p)y-667__ 4gb 512 meg x 72 5.3 gb/s 3.0n s/667 mt/s 5-5-5 mt36hvs51272(p)y-53e__ 4gb 512 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 table 5: part numbers and timing paramete rs ? 4gb modules with heat spreader base device: mt47h512m4thn, 1 2gb twindie ddr2 sdram part number ,2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvzs51272(p)y-80e__ 4gb 512 meg x 72 6.2 gb/s 2.5n s/800 mt/s 5-5-5 mt36hvzs51272(p)y-800__ 4gb 512 meg x 72 6.2 gb/s 2.5n s/800 mt/s 6-6-6 mt36hvzs51272(p)y-667__ 4gb 512 meg x 72 5.3 gb/s 3.0n s/667 mt/s 5-5-5 mt36hvzs51272(p)y-53e__ 4gb 512 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 3 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 54 is nc for 2gb and ba2 for 4gb. 2. pin 55 is nc for nonparity and e rr _o ut for parity. 3. pin 68 is nc for nonparity and p ar _i n for parity. table 6: pin assignments 240-pin ddr2 vlp rdimm front 240-pin ddr2 vlp rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 31 dq19 61 a4 91 v ss 121 v ss 151 v ss 181 v dd q211 dqs14 2v ss 32 v ss 62 v dd q 92 dqs5# 122 dq4 152 dq28 182 a3 212 dqs14# 3 dq0 33 dq24 63 a2 93 dqs5 123 dq5 153 dq29 183 a1 213 v ss 4 dq1 34 dq25 64 v dd 94 v ss 124 v ss 154 v ss 184 v dd 214 dq46 5v ss 35 v ss 65 v ss 95 dq42 125 dqs9 155 dqs12 185 ck0 215 dq47 6 dqs0# 36 dqs3# 66 v ss 96 dq43 126 dqs9# 156 dqs12# 186 ck0# 216 v ss 7 dqs0 37 dqs3 67 v dd 97 v ss 127 v ss 157 v ss 187 v dd 217 dq52 8v ss 38 v ss 68 3 nc/ p ar _i n 98 dq48 128 dq6 158 dq30 188 a0 218 dq53 9 dq2 39 dq26 69 v dd 99 dq49 129 dq7 159 dq31 189 v dd 219 v ss 10 dq3 40 dq27 70 a10 100 v ss 130 v ss 160 v ss 190 ba1 220 rfu 11 v ss 41 v ss 71 ba0 101 sa2 131 dq12 161 cb4 191 v dd q221 rfu 12 dq8 42 cb0 72 v dd q 102 nc 132 dq13 162 cb5 192 ras# 222 v ss 13 dq9 43 cb1 73 we# 103 v ss 133 v ss 163 v ss 193 s0# 223 dqs15 14 v ss 44 v ss 74 cas# 104 dqs6# 134 dqs10 164 dqs17 194 v dd q 224 dqs15# 15 dqs1# 45 dqs8# 75 v dd q 105 dqs6 135 dqs10# 165 dqs17# 195 odt0 225 v ss 16 dqs1 46 dqs8 76 s1# 106 v ss 136 v ss 166 v ss 196 a13 226 dq54 17 v ss 47 v ss 77 odt1 107 dq50 137 rfu 167 cb6 197 v dd 227 dq55 18 reset# 48 cb2 78 v dd q 108 dq51 138 rfu 168 cb7 198 v ss 228 v ss 19 nc 49 cb3 79 v ss 109 v ss 139 v ss 169 v ss 199 dq36 229 dq60 20 v ss 50 v ss 80 dq32 110 dq56 140 dq14 170 v dd q 200 dq37 230 dq61 21 dq10 51 v dd q 81 dq33 111 dq57 141 dq15 171 cke1 201 v ss 231 v ss 22 dq11 52 cke0 82 v ss 112 v ss 142 v ss 172 v dd 202 dqs13 232 dqs16 23 v ss 53 v dd 83 dqs4# 113 dqs7# 143 dq20 173 a14 203 dqs13# 233 dqs16# 24 dq16 54 1 nc/ba2 84 dqs4 114 dqs7 144 dq21 174 a15 204 v ss 234 v ss 25 dq17 55 2 nc/ e rr _o ut 85 v ss 115 v ss 145 v ss 175 v dd q 205 dq38 235 dq62 26 v ss 56 v dd q 86 dq34 116 dq58 146 dqs11 176 a12 206 dq39 236 dq63 27 dqs2# 57 a11 87 dq35 117 dq59 147 dqs11# 177 a9 207 v ss 237 v ss 28 dqs2 58 a7 88 v ss 118 v ss 148 v ss 178 v dd 208 dq44 238 v ddspd 29 v ss 59 v dd 89 dq40 119 sda 149 dq22 179 a8 209 dq45 239 sa0 30 dq18 60 a5 90 dq41 120 scl 150 dq23 180 a6 210 v ss 240 sa1
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 4 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments and descriptions table 7: pin descriptions symbol type description a[15:0] input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write co mmands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba[2:0]) or all device banks (a10 high). the address inputs also provide the op- code during a load mode co mmand. a[13:0] (2gb, 4gb). a[ 15:14] are connected for parity. ba[2:0] input bank address inputs: ba[2/1:0] define the device ba nk to which an active, read, write, or precharge command is being applied. ba[2/1:0] define which mode register (mr, emr1, emr2, and emr3) is loaded during the load mode command. ba[1:0] (2gb), ba[2:0] (4gb). ck0, ck0# input clock: ck and ck# are differential clock inputs . all control, command , and address input signals are sampled on the crossi ng of the positive edge of ck and the negative edge of ck#. output data (dq, dqs, and dqs#) is referenced to the crossings of ck and ck#. cke[1:0] input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and clocks on the ddr2 sdram. odt[1:0] input on-die termination: odt enables (registered high) and disables (registered low) termination resista nce internal to the ddr2 sdram. wh en enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. p ar _i n input parity input: parity bit for the address, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s#[1:0] input chip select: s# enables (registered low) and di sables (registered high) the command decoder. sa[2:0] input serial address inputs: these pins are used to conf igure the spd eeprom device. scl input serial clock for spd eeprom: scl is used to synchronize communication to and from the spd eeprom. cb[7:0] i/o check bits. dq[63:0] i/o data input/output: bidirectional data bus. dqs[17:0], dqs#[17:0] i/o data strobe: dqs# is only used when differential data strobe mode is enabled via the load mode command. output with read data. edge-aligned with read data. input with write data. center-alig ned with write data. sda i/o serial data: sda is a bidirectional pin used to tran sfer addresses and data into and out of the sda eeprom portion of the module. e rr _o ut output (open drain) parity error output: parity error found on the command and address bus. v dd /v dd q supply power supply (1.8v 0.1v): the component v dd and v dd q are connected to the module v dd . v ddspd supply serial eeprom power supply: +1.7v to +3.6v. v ref supply reference voltage: v dd /2. vss supply ground. nc ? no connect: these pins are not connected on the module. rfu ? reserved for future use.
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 5 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm functional block diagram functional block diagram figure 2: functional block diagram dm cs# dqs dqs# dq dq dq dq dq0 dq1 dq2 dq3 dq dq dq dq u1b u1t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq4 dq5 dq6 dq7 dq dq dq dq u22b u22t dm cs# dqs dqs# dqs0 dqs0# dqs9 dqs9# dm cs# dqs dqs# dq dq dq dq dq8 dq9 dq10 dq11 dq dq dq dq u2b u2t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq12 dq13 dq14 dq15 dq dq dq dq u21b u21t dm cs# dqs dqs# dqs1 dqs1# dqs10 dqs10# dm cs# dqs dqs# dq dq dq dq dq16 dq17 dq18 dq19 dq dq dq dq u3b u3t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq20 dq21 dq22 dq23 dq dq dq dq u20b u20t dm cs# dqs dqs# dqs2 dqs2# dqs11 dqs11# dm cs# dqs dqs# dq dq dq dq dq24 dq25 dq26 dq27 dq dq dq dq u4b u4t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq28 dq29 dq30 dq31 dq dq dq dq u19b u19t dm cs# dqs dqs# dqs3 dqs3# dqs12 dqs12# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq32 dq33 dq34 dq35 dq dq dq dq u9b u9t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq36 dq37 dq38 dq39 dq dq dq dq u15b u15t dm cs# dqs dqs# dqs4 dqs4# dqs13 dqs13# dm cs# dqs dqs# dq dq dq dq dq40 dq41 dq42 dq43 dq dq dq dq u10b u10t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq44 dq45 dq46 dq47 dq dq dq dq u14b u14t dm cs# dqs dqs# dqs5 dqs5# dqs14 dqs14# dm cs# dqs dqs# dq dq dq dq dq48 dq49 dq50 dq51 dq dq dq dq u11b u11t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq52 dq53 dq54 dq55 dq dq dq dq u13b u13t dm cs# dqs dqs# dqs6 dqs6# dqs15 dqs15# dm cs# dqs dqs# dq dq dq dq dq56 dq57 dq58 dq59 dq dq dq dq u8b u8t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq60 dq61 dq62 dq63 dq dq dq dq u16b u16t dm cs# dqs dqs# dqs7 dqs7# dqs16 dqs16# a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp r e g i s t e r s pll s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 p ar _i n reset# rs0#: rank 0 rs1#: rank 1 rba[2:0]: ddr2 sdram ra[13:0]: ddr2 sdram rras#: ddr2 sdram rcas#: ddr2 sdram rwe#: ddr2 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 e rr _o ut ck0 ck0# ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 register x 2 reset# u6 v ref v ss ddr2 sdram ddr2 sdram v dd /v dd q spd eeprom ddr2 sdram u7, u17 u12 v ss rs0# rs1# cb0 cb1 cb2 cb3 u5b u5t cb4 cb5 cb6 cb7 u18b dqs8 dqs8# dqs17 dqs17# u18t rank 0 = u1b?u5b, u8b?u11b, u13b?u16b, u18b?u22b rank 1 = u1t?u5t, u8t?u11t, u13t?u16t, u18t?u22t v ss v ddspd
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 6 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm general description general description the mt36hvs25672(p), mt36hvs51272(p), and mt36hvzs51272(p) ddr2 sdram modules are high-speed, cmos dynamic random access 2gb and 4gb memory modules organized in a x72 configuration. these ddr2 sdram modules use internally configured, 4-bank (2gb) or 8-bank (4gb) ddr2 twin die sdram devices. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. clock, control, command, and address signals are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. register and pll operation these ddr2 sdram modules operate in re gistered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the register(s) and pll reduce clock, control, command, and address signals load ing by isolating dram from the system controller. pll clock timing is defined by jedec specifications and ensured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. serial presence-d etect operation ddr2 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are progra mmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/eeprom addr esses. write protect (wp) is connected to v ss , permanently disabling hardware write protect.
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 7 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 8 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. the refresh rate is requ ired to double when 85c < t c 95c. 2. for further information, refer to technical note tn-00-08: ?thermal applications ,? available on micron?s web site. table 8: absolute maximum ratings symbol parameter min max units v dd /v dd qv dd /v dd q supply voltage relative to v ss ?0.5 2.3 v v in , v out voltage on any pin relative to v ss ?0.5 2.3 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, s#, cke, ba, odt ?10 10 a ck, ck# ?250 250 i oz output leakage current; 0v v out v dd q; dq and odt are disabled dq, dqs, dqs# ?10 10 a i vref v ref leakage current; v ref = v alid v ref level ?72 72 a t a module ambient operating temperature commercial 0 +70 c industrial ?40 +85 c t c 1 ddr2 sdram component case operating temperature 2 commercial 0 +85 c industrial ?40 +95 c
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 8 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 9. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 9: module and component speed grades ddr2 components may exceed th e listed module speed grades module speed grade component speed grade -80e -25e -800 -25 -667 -3 -53e -37e
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 9 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications i dd specifications notes: 1. value calculated as one mo dule rank in this op erating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. table 10: ddr2 i dd specifications and conditions ? 2gb values are for the mt47h256m4 ddr2 sdram only and are computed from values specified in the 1gb twindie (256 meg x 4) component data sheet parameter/condition symbol -667 -53e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 1 1,836 1,656 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is the same as i dd 4w i dd 1 1 2,106 1,926 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs ar e stable; data bus inputs are floating i dd 2p 2 252 252 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus in puts are stable; data bus inputs are floating i dd 2q 2 1,026 936 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd 2n 2 1,116 1,026 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other con trol and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3pf 2 756 666 ma slow pdn exit mr[12] = 1 i dd 3ps 2 342 342 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd 3n 2 1,386 1,206 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 3,276 2,736 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 3,456 2,826 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd 5 2 3,456 3,276 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd 6 2 252 252 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stabl e during deselects; data bus inputs are switching i dd 7 1 4,536 4,266 ma
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 10 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications notes: 1. value calculated as one mo dule rank in this op erating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. table 11: ddr2 i dd specifications and conditions ? 4gb values are for the mt47h512m4 ddr2 sdram only and are computed from values specified in the 2gb twindie (512 meg x 4) component data sheet parameter/condition symbol -80e/ -800 -667 -53e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 0 1 1,836 1,746 1,476 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be tween valid comma nds; address bus inputs are switching; data pattern is the same as i dd 4w i dd 1 1 2,196 2,016 1,926 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus in puts are stable; da ta bus inputs are floating i dd 2p 2 252 252 252 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are stable; data bus inputs are floating i dd 2q 2 1,026 846 846 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bu s inputs are switching; data bus inputs are switching i dd 2n 2 1,116 936 936 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3pf 2 846 666 666 ma slow pdn exit mr[12] = 1 i dd 3ps 2 306 306 306 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus in puts are switching; data bus inputs are switching i dd 3n 2 1,296 1,206 1,026 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 2,826 2,376 2,196 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 2,826 2,376 2,196 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd 5 2 4,446 4,086 3,996 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; da ta bus inputs are floating i dd 6 2 252 252 252 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inpu ts are stable during deselects; data bus inputs are switching i dd 7 1 6,246 5,256 5,076 ma
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 11 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications register and pll specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr2 sdram rdimms. these are mean t to be a subset of the parameters for the specific device used on th e module. detailed information for this register is available in jedec standard jesd82. table 12: register specifications sstu32868 devices or equivalent jesd82-17 parameter symbol pins condition min max units dc high-level input voltage v ih ( dc ) control, command, address sstl_18 v ref ( dc ) + 125 v dd q + 250 mv dc low-level input voltage v il ( dc ) control, command, address sstl_18 0 v ref ( dc ) - 125 mv ac high-level input voltage v ih ( ac ) control, command, address sstl_18 v ref ( dc ) + 250 v dd mv ac low-level input voltage v il ( ac ) control, command, address sstl_18 0 v ref ( dc ) - 250 mv output high voltage v oh parity output lvcmos 1.2 ? v output low voltage v ol parity output lvcmos ? 0.5 v input current i i all pins v i = v dd q or v ss q?5 5a static standby i dd all pins reset# = v ss q (i o = 0) ? 100 a static operating i dd all pins reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) i o = 0 ?80ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle ?varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle ?varies by manufacturer a input capacitance (per device, per pin) c i all inputs except reset# v i = v ref 250mv; v dd q = 1.8v 2.5 4 pf input capacitance (per device, per pin) c i reset# v i = v dd q or v ss q?varies by manufacturer pf
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 12 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications notes: 1. pll timing and swit ching specifications are critical for proper operation of the ddr2 dimm. this is a subset of parameters for the specific pll used. detailed pll in formation is available in jedec standard jesd82. table 13: pll specifications cu877 device or equivalent jesd82-8.01 parameter symbol pins condition min max units dc high-level input voltage v ih reset# lvcmos 0.65 v dd ?v dc low-level input voltage v il reset# lvcmos ? 0.35 v dd v input voltage (limits) v in reset#, ck, ck# ? ?0.3 v dd q + 0.3 v dc high-level input voltage v ih ck, ck# differential input 0.65 v dd ?v dc low-level input voltage v il ck, ck# differential input ? 0.35 v dd v input differential-pair cross voltage v ix ck, ck# differential input (v dd q/2) - 0.15 (v dd q/2) + 0.15 v input differential voltage v id ( dc ) ck, ck# differential input 0.3 v dd q + 0.4 v input differential voltage v id ( ac ) ck, ck# differential input 0.6 v dd q + 0.4 v input current i i reset# v i = v dd q or v ss q ?10 10 a ck, ck# v i = v dd q or v ss q?250+250a output disabled current i odl ? reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) 100 ? a static supply current i ddld ? ck = ck# = low ? 500 a dynamic supply i dd n/a ck, ck# = 270 mhz, all outputs open (not connected to pcb) ?300ma input capacitance c in each input v i = v dd q or v ss q2 3pf table 14: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l? 15s input clock slew rate t slr(i) 1.0 4 v/ns ssc modulation frequency ? 30 33 khz ssc clock input frequency deviation ? 0.0 ?0.5 % pll loop bandwidth (?3db from unity gain) ? 2.0 ? mhz
pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 13 ?2006 micron technology, inc. all rights reserved 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/spd . table 15: serial presence-detect eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.1 3.0 a output leakage current: v out = gnd to v dd i lo 0.05 3.0 a standby current i sb 1.6 4.0 a power supply curren t, read: scl clock frequency = 100 khz i cc r 0.4 1.0 ma power supply current, write: scl clock frequency = 100 khz i cc w 2.0 3.0 ma table 16: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda fall time t f?300ns2 sda rise time t r?300ns2 data-in hold time t hd:dat 0 ? s start condition hold time t h:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, the micron logo, and twindie are trademarks of micron technology, inc. all other trademarks are the propert y of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm module dimensions pdf: 09005aef826947c6/source: 09005aef825e878c micron technology, inc., reserves the right to change products or specifications without notice. hvs36c256_512x72.fm - rev. c 4/08 en 14 ?2006 micron technology, inc. all rights reserved. module dimensions figure 3: 240-pin ddr2 vlp rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 18.05 (0.711) 17.75 (0.699) pin 1 2.5 (0.098) d (2x) 2.3 (0.091) typ 5 (0.25) typ 123 (4.84) typ 1.0 (0.039) typ 2.2 (0.087) typ 0.8 (0.04) typ 2.0 (0.079) r (4x) 0.75 (0.029) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 63.0 (2.48) typ 55.0 (2.16) typ 10.0 (0.394) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 3.99 (0.157) max 1.0 (0.039) typ 3.05 (0.012) typ 70.68 (2.78) typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u6 u6 u6 u7 u7 u7 u12 u13 u13 u14 u14 u15 u15 u16 u16 u17 u17 u17 u18 u18 u19 u19 u20 u20 u21 u21 u22 u22 1.37 (0.054) 1.17 (0.046) 9.1 (0.358) max with heat spreader attached

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